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September 2006
HYS64D32301HU-[5/6]-C HYS[7 2/64]D 64 3 0 0 H U- [ 5 / 6 ] - C HYS[64/72]D128320HU-[5/6]-C
184-Pin Unbuffered Double Data Rate SDRAM UDIMM DDR SDRAM RoHS Compliant Products
Internet Data Sheet
Rev. 1.21
Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
HYS64D32301HU-[5/6]-C, HYS[72/64]D64300HU-[5/6]-C, HYS[64/72]D128320HU-[5/6]-C Revision History: 2006-09, Rev. 1.21 Page All 14 26 Subjects (major changes since last revision) Adapted internet edition changed component configuration for 256MB to 32M x16 changed DDR400 tRFC from 70 ns to 65 ns
Previous Revision: Rev. 1.20, 2005-12
Previous Revision: Rev. 1.10, 2005-05
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 03292006-RA8T-MSZL
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
1
Overview
This chapter gives an overview of the 184-Pin Unbuffered Double Data Rate SDRAM product family and describes its main characteristics.
1.1
Features
* 184-Pin Unbuffered Double Data Rate SDRAM (ECC and non-parity) for PC and Workstation main memory applications * One rank 32M x64, 64M x64, 64M x72 ,and two ranks 128M x64 ,128M x72 organization * Standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (0.2V) and +2.6V (0.1V) power supply for DDR400 * Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) * Auto Refresh (CBR) and Self Refresh * RAS-lockout supported tRAP=tRCD * All inputs and outputs SSTL_2 compatible * Serial Presence Detect with E2PROM * Standard MO-206 form factor: 133.35 mm x 31.75 mm x 4.00 mm max. * Standard reference layout for raw cards: A, B and C * Gold plated contacts * RoHS Compliant Product1)
TABLE 1
Performance
Part Number Speed Code Speed Grade max. Clock Frequency Component Module @CL3 @CL2.5 @CL2 -5 DDR400B PC3200-3033 -6 DDR333B PC2700-2533 166 166 133 Unit -- -- MHz MHz MHz
fCK3 fCK2.5 fCK2
200 166 133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
1.2
Description
designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using the 2pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer
The HYS64D32301HU-[5/6]-C, HYS[72/64]D64300HU- [5/6]-C, HYS[64/72]D128320HU-[5/6]-C, and are industry standard 184-Pin Unbuffered Double Data Rate SDRAM (UDIMM) organized as 32M x 64 (256 MB), 64M x 64 (512 MB), 128M x 64 (1 GB) for non-parity and 64M x 72 (512 MB), 128M x 72 (1 GB) for ECC main memory applications. The memory array is
TABLE 2
Ordering Information for Lead-Free Products (RoHSCompliant Product)
Product Type
1)
Compliance Code2) PC3200U-30331-C3 PC3200U-30331-A1 PC3200U-30331-A1 PC3200U-30331-B2 PC3200U-30331-B2 PC2700U-25331-C3 PC2700U-25331-A1 PC2700U-25331-A1 PC2700U-25331-B2 PC2700U-25331-B2
Description one rank 256 MB DIMM one rank 512 MB DIMM one rank 512 MB ECC-DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM one rank 256 MB DIMM one rank 512 MB DIMM one rank 512 MB ECC-DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM
SDRAM Technology 512 Mbit (x16) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x16) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8)
PC3200 (CL=3.0) HYS64D32301HU-5-C HYS64D64300HU-5-C HYS72D64300HU-5-C HYS64D128320HU-5-C HYS72D128320HU-5-C PC2700 (CL=2.5) HYS64D32301HU-6-C HYS64D64300HU-6-C HYS72D64300HU-6-C HYS64D128320HU-6-C HYS72D128320HU-6-C
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D128320HU-5-C, indicating Rev.C die are used for SDRAM components. 2) The Compliance Code is printed on the module labels and describes the speed sort (for example "PC3200"), the latencies (for example "30330" means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC SPD code definition version 0, and the Raw Card used for this module.
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
2
Pin Configuration
and Table 5 respectively. The pin numbering is depicted in Figure 1.
The pin configuration of the Unbuffered DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4
TABLE 3
Pin Configuration of UDIMM
Pin# Name Pin Type I NC I I I NC I I I I NC I I NC I I I I I Buffer Type SSTL - SSTL SSTL SSTL - SSTL SSTL SSTL SSTL - SSTL SSTL - SSTL SSTL SSTL SSTL SSTL Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module Note: 1-rank module Chip Select Rank 0 Chip Select Rank 1 Note: 2-rank module Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable Bank Address Bus 2:0 Complement Clock Signals 2:0 Function
Clock Signals 137 16 76 138 17 75 21 111 CK0 NC CK1 CK2 CK0 NC CK1 CK2 CKE0 CKE1 NC Control Signals 157 158 S0 S1 NC 154 65 63 59 52 RAS CAS WE BA0 BA1 Clock Signals 2:0
Address Signals
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin# 48 43 41 130 37 32 125 29 122 27 141 118 115
Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 NC
Pin Type I I I I I I I I I I I I I I NC I NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL -
Function Address Bus 11:0
Address Bus 11:0
Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: 128 Mbit based module Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies
167
A13 NC
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin#
Name
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function
Data Signals 2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 Data Bus 63:0
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin# 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175
Name DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin# 178 179 44 45 49 51 134 135 142 144 5 14 25 36 56 67 78 86 47 97 107 119 129 149 159 169 177 140 EEPROM 92
Name DQ62 DQ63 CB0 NC CB1 NC CB2 NC CB3 NC CB4 NC CB5 NC CB6 NC CB7 NC DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 NC DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 NC SCL
Pin Type I/O I/O I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I I I I I I I I I NC I
Buffer Type SSTL SSTL SSTL - SSTL - SSTL - SSTL - SSTL - SSTL - SSTL - SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - CMOS
Function Data Bus 63:0 Check Bit 0 Check Bit 1 Check Bit 2 Check Bit 3 Check Bit 4 Check Bit 5 Check Bit 6 Check Bit 7 Data Strobe Bus 7:0
Data Strobe 8 Data Mask Bus 7:0
Data Mask 8
Serial Bus Clock
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin# 91 181 182 183 1 184 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, 120, 148, 168
Name SDA SA0 SA1 SA2 VREF VDDSPD VDDQ
Pin Type I/O I I I AI PWR PWR
Buffer Type OD CMOS CMOS CMOS - - -
Function Serial Bus Data Slave Address Select Bus 2:0
Power Supplies I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply
VDD
PWR
-
Power Supply
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin# 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 Other Pins 82 9, 10, 71, 90, 101, 102, 103, 113, 163, 173
Name VSS
Pin Type GND
Buffer Type -
Function Ground Plane
VDDID NC
O NC
OD -
VDD Identification Not connected
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
TABLE 4
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 5
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
FIGURE 1
Pin Configuration 184-Pin, UDIMM
Notes 1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 3 5 %
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
TABLE 6
Address Format
Density 256 MB 512 MB 512 MB 1 GB 1 GB Organization 32M x64 64M x64 64M x72 128M x64 128M x72 Memory Ranks 1 1 1 2 2 SDRAMs 32M x16 64M x8 64M x8 64M x8 64M x8 # of SDRAMs 4 8 9 16 18 # of row/bank/ columns bits 13/2/10 13/2/11 13/2/11 13/2/11 13/2/11 Refresh 8K 8K 8K 8K 8K Period 64 ms 64 ms 64 ms 64 ms 64 ms Interval 7.8 ms 7.8 ms 7.8 ms 7.8 ms 7.8 ms
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
3
3.1
Electrical Characteristics
Operating Conditions
TABLE 12
Absolute Maximum Ratings
Parameter
Symbol min.
Values typ. - - - - - - 1 50 max.
Unit
Note/ Test Condition - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG
PD
-0.5 -1 -1 -1 0 -55 - -
VDDQ + 0.5
+3.6 +3.6 +3.6 +70 +150 - -
V V V V C C W mA
IOUT
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
TABLE 13
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Min. Device Supply Voltage Device Supply Voltage Output Supply Voltage Output Supply Voltage EEPROM supply voltage Supply Voltage, I/O Supply Voltage Input Reference Voltage I/O Termination Voltage (System) VDD VDD VDDQ VDDQ VDDSPD VSS, VSSQ VREF VTT 2.3 2.5 2.3 2.5 2.3 0 0.49 x VDDQ VREF - 0.04 0.5 x VDDQ Values Typ. 2.5 2.6 2.5 2.6 2.5 Max. 2.7 2.7 2.7 2.7 3.6 0 0.51 x VDDQ VREF + 0.04 V V V V V V V V fck 166 MHz fck 166 MHz 2) fck 166 MHz 3) fck 166 MHz 2)3) -- --
4) 5)
Unit Note/Test Condition 1)
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Parameter
Symbol Min.
Values Typ. Max. VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.4 2
Unit Note/Test Condition 1)
Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current
VIH(DC) VIL(DC) VIN(DC) VID(DC) VIRatio II
VREF + 0.15 -0.3 -0.3 0.36 0.71 -2
V V V V -- A
6) 6) 6)
6)7)
8)
Any input 0 V VIN VDD; All other pins not under test = 0 V 9) DQs are disabled; 0 V VOUT VDDQ 9) VOUT = 1.95 V VOUT = 0.35 V
Output Leakage Current
IOZ
-5 -- 16.2
5 -16.2 --
A mA mA
Output High Current, Normal IOH Strength Driver Output Low Current, Normal Strength Driver
1) 2) 3) 4) 5) 6) 7) 8)
IOL
9)
0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V; VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400); DDR400 conditions apply for all clock frequencies above 166 MHz Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Values are shown per pin.
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
3.2
IDD Specification and Conditions
TABLE 14
IDD Conditions
Parameter Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet.
Symbol
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
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TABLE 15
IDD Specification for HYS[64/72]D[32/64/128]3xxHU-5-C
HYS64D128320HU-5-C HYS64D32301HU-5-C HYS64D64300HU-5-C HYS72D64300HU-5-C Product Type HYS72D128320HU-5-C Unit Note 1)2)
Organization
256MB x64 1 Rank -5
512MB x64 1 Rank -5 Max. 360 440 18 120 90 60 180 540 540 760 20 1000 Typ. 480 560 9 200 140 100 280 640 680 1160 13 1560 Max. 600 680 37 240 180 130 340 720 760 1520 40 1840
512MB x72 1 Rank -5 Typ. 540 630 10 230 150 110 320 720 770 1310 14 1760 Max. 680 770 41 270 210 140 380 810 860 1710 45 2070
1GB x64 2 Ranks -5 Typ. 760 840 18 400 270 190 560 920 960 1440 26 1840 Max. 940 1020 74 480 370 260 670 1060 1100 1860 80 2180
1GB x72 2 Ranks -5 Typ. 860 950 20 450 310 220 630 1040 1080 620 29 2070 Max. 1050 1140 83 540 410 290 760 1190 1230 2090 90 2450 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
Typ. 300 360 4 100 70 50 150 440 460 580 6 840
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
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TABLE 16
IDD Specification for HYS[64/72]D[32/64/128]3xxHU-6-C
HYS64D128320HU-6-C HYS64D32301HU-6-C HYS64D64300HU-6-C HYS72D64300HU-6-C Product Type HYS72D128320HU-6-C Unit Note 1)2)
Organization
256MB x64 1 Rank -6
512MB x64 1 Rank -6 Max. 340 380 18 100 90 60 160 460 480 700 20 920 Typ. 480 520 9 170 120 90 260 560 600 1040 12.8 1400 Max. 560 640 37 200 180 120 300 680 720 1400 40 1640
512MB x72 1 Rank -6 Typ. 540 590 10 190 140 100 290 630 680 1170 14.4 1580 Max. 630 720 41 230 200 140 330 770 810 1580 45 1850
1GB x64 2 Ranks -6 Typ. 740 780 18 340 240 180 510 820 860 1300 25.6 1660 Max. 860 940 74 400 350 240 590 980 1020 1700 80 1940
1GB x72 2 Ranks -6 Typ. 830 870 20 380 270 200 580 920 960 1460 28.8 1860 Max. 960 1050 83 450 400 270 670 1100 1140 1910 90 2180 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
Typ. 280 320 4 80 60 40 130 380 400 520 6.4 760
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.6 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
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3.3
AC Characteristics
TABLE 17
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol
-5 DDR400B Min. Max. +0.5 0.55 8 12 12 0.55
-6 DDR333 Min. -0.7 0.45 6 6 7.5 0.45 Max. +0.7 0.55 12 12 12 0.55
Unit
Note/ Test Condition 1)
DQ output access time from CK/CK CK high-level width Clock cycle time
tAC tCH tCK
-0.7 0.45 5 6 7.5
ns tCK ns ns ns tCK tCK
2)3)4)5)
2)3)4)5)
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5)6)
CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access time from CK/CK
tCL tDAL tDH tDIPW tDQSCK
0.45
(tWR/tCK) + (tRP/tCK) 0.4 1.75 -0.5 0.35 -- 0.72 0.4 0.2 0.2 min. (tCL, tCH) -- -- +0.5 -- +0.40 1.25 -- -- -- -- +0.7 0.6 0.7 -- -- -- 0.45 1.75 -0.6 0.35 -- 0.75 0.45 0.2 0.2 min. (tCL, tCH) -0.7 0.75 0.8 2.2 -- -- +0.6 -- +0.45 1.25 -- -- -- -- +0.7 -- -- --
ns ns ns tCK ns tCK ns tCK tCK ns ns ns ns ns
2)3)4)5) 2)3)4)5)6)
2)3)4)5)
DQS input low (high) pulse width tDQSL,H (write cycle) DQS-DQ skew (DQS and associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Clock Half Period Data-out high-impedance time from CK/CK Address and control input hold time tDQSQ tDQSS tDS tDSH tDSS tHP tHZ tIH
2)3)4)5)
TSOPII 2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5)7)
fast slew rate
3)4)5)6)8)
slow slew rate
3)4)5)6)8) 2)3)4)5)9)
Control and Addr. input pulse width (each input)
tIPW
2.2
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Parameter
Symbol
-5 DDR400B Min. Max. -- -- +0.7 -- -- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- -- --
-6 DDR333 Min. 0.75 0.8 -0.7 2 tHP - tQHS -- tRCD 42 60 18 -- 72 18 0.9 0.40 12 0.25 0 0.40 15 1 75 200 Max. -- -- +0.7 -- -- +0.55 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- -- --
Unit
Note/ Test Condition 1)
Address and control input setup time
tIS
0.6 0.7
ns ns ns tCK ns ns ns ns ns ns s ns ns tCK tCK ns tCK ns tCK ns tCK ns tCK
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5)7)
Data-out low-impedance time from CK/CK Mode register set command cycle time DQ/DQS output hold time Data hold skew factor Active to Autoprecharge delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay Average Periodic Refresh Interval Auto-refresh to Active/Autorefresh command period Precharge command period Read preamble Read postamble Active bank A to Active bank B command Write preamble Write preamble setup time Write postamble Write recovery time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command
tLZ tMRD tQH tQHS tRAP tRAS tRC tRCD tREFI tRFC tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR tXSNR tXSRD
-0.7 2 tHP - tQHS -- tRCD 40 55 15 -- 65 15 0.9 0.40 10 0.25 0 0.40 15 2 75 200
2)3)4)5)
2)3)4)5)
TSOPII 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)8)
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)11) 2)3)4)5)12) 2)3)4)5) 2)3)4)5)
2)3)4)5)
2)3)4)5)
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 18 "SPD Codes for HYS64D32301HU-[5/6]-C" on Page 29 * Table 19 "SPD Codes for HYS[72/64]D64300HU-[5/6]-C" on Page 32 * Table 20 "SPD Codes for HYS[64/72]D128320HU-[5/6]-C" on Page 36
TABLE 18
SPD Codes for HYS64D32301HU-[5/6]-C
Product Type Organization HYS64D32301HU-5-C 256MB x64 1 Rank (x16) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Description Programmed SPD Bytes in E PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency
2
HYS64D32301HU-6-C 256MB x64 1 Rank (x16) PC2700U-25331 Rev. 1.0 HEX 80 08 07 0D 0A 01 40 00 04 60 70 00 82 10 00 01 0E 04 0C 01
PC3200U-30331 Rev. 1.0 HEX 80 08 07 0D 0A 01 40 00 04 50 70 00 82 10 00 01 0E 04 1C 01
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Product Type Organization
HYS64D32301HU-5-C 256MB x64 1 Rank (x16)
HYS64D32301HU-6-C 256MB x64 1 Rank (x16) PC2700U-25331 Rev. 1.0 HEX 02 20 C1 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 2D 55 00 01 00 10 1A 7F 7F 7F 7F 7F 51
Label Code JEDEC SPD Revision Byte# 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 Description Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6)
PC3200U-30331 Rev. 1.0 HEX 02 20 C1 60 70 75 70 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 01 00 10 76 7F 7F 7F 7F 7F 51
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Product Type Organization
HYS64D32301HU-5-C 256MB x64 1 Rank (x16)
HYS64D32301HU-6-C 256MB x64 1 Rank (x16) PC2700U-25331 Rev. 1.0 HEX 00 00 xx 36 34 44 33 32 33 30 31 48 55 36 43 20 20 20 20 20 20 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC3200U-30331 Rev. 1.0 HEX 00 00 xx 36 34 44 33 32 33 30 31 48 55 35 43 20 20 20 20 20 20 1x xx xx xx xx 00
99 - 127 Not used
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HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
TABLE 19
SPD Codes for HYS[72/64]D64300HU-[5/6]-C
HYS64D64300HU-5-C HYS64D64300HU-6-C HYS72D64300HU-5-C Product Type HYS72D64300HU-6-C 512MB x72 1 Rank (x8) PC2700U- 25331 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1 75
Organization
512MB x64 1 Rank (x8)
512MB x64 1 Rank (x8) PC2700U- 25331 Rev. 1.0 HEX 80 08 07 0D 0B 01 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1 75
512MB x72 1 Rank (x8) PC3200U- 30331 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 50 70 02 82 08 08 01 0E 04 1C 01 02 20 C1 60
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Description Programmed SPD Bytes in E PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns]
2 2
PC3200U- 30331 Rev. 1.0 HEX 80 08 07 0D 0B 01 40 00 04 50 70 00 82 08 00 01 0E 04 1C 01 02 20 C1 60
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
HYS64D64300HU-5-C
HYS64D64300HU-6-C
HYS72D64300HU-5-C
Product Type
Organization
512MB x64 1 Rank (x8)
512MB x64 1 Rank (x8) PC2700U- 25331 Rev. 1.0 HEX 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 01 00 10 53 7F 7F 7F
512MB x72 1 Rank (x8) PC3200U- 30331 Rev. 1.0 HEX 70 75 70 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 00 10 C1 7F 7F 7F
512MB x72 1 Rank (x8) PC2700U- 25331 Rev. 1.0 HEX 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 01 00 10 65 7F 7F 7F
Label Code JEDEC SPD Revision Byte# 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 Description tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3)
PC3200U- 30331 Rev. 1.0 HEX 70 75 70 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 00 10 AF 7F 7F 7F
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HYS72D64300HU-6-C
Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
HYS64D64300HU-5-C
HYS64D64300HU-6-C
HYS72D64300HU-5-C
Product Type
Organization
512MB x64 1 Rank (x8)
512MB x64 1 Rank (x8) PC2700U- 25331 Rev. 1.0 HEX 7F 7F 51 00 00 xx 36 34 44 36 34 33 30 30 48 55 36 43 20 20 20 20 20 20 1x xx
512MB x72 1 Rank (x8) PC3200U- 30331 Rev. 1.0 HEX 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 48 55 35 43 20 20 20 20 20 20 1x xx
512MB x72 1 Rank (x8) PC2700U- 25331 Rev. 1.0 HEX 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 48 55 36 43 20 20 20 20 20 20 1x xx
Label Code JEDEC SPD Revision Byte# 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Description Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code
PC3200U- 30331 Rev. 1.0 HEX 7F 7F 51 00 00 xx 36 34 44 36 34 33 30 30 48 55 35 43 20 20 20 20 20 20 1x xx
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HYS72D64300HU-6-C
Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
HYS64D64300HU-5-C
HYS64D64300HU-6-C
HYS72D64300HU-5-C
Product Type
Organization
512MB x64 1 Rank (x8)
512MB x64 1 Rank (x8) PC2700U- 25331 Rev. 1.0 HEX xx xx xx 00
512MB x72 1 Rank (x8) PC3200U- 30331 Rev. 1.0 HEX xx xx xx 00
512MB x72 1 Rank (x8) PC2700U- 25331 Rev. 1.0 HEX xx xx xx 00
Label Code JEDEC SPD Revision Byte# 93 94 95 - 98 Description Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC3200U- 30331 Rev. 1.0 HEX xx xx xx 00
99 - 127 Not used
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HYS72D64300HU-6-C
Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
TABLE 20
SPD Codes for HYS[64/72]D128320HU-[5/6]-C
HYS64D128320HU-5-C HYS64D128320HU-6-C HYS72D128320HU-5-C Product Type HYS72D128320HU-6-C 1 GByte x72 PC2700U- 25331 Rev. 1.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1
Organization
1 GByte x64
1 GByte x64
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
2
PC3200U- 30331 Rev. 1.0 HEX 80 08 07 0D 0B 02 40 00 04 50 70 00 82 08 00 01 0E 04 1C 01 02 20 C1
PC2700U- 25331 Rev. 1.0 HEX 80 08 07 0D 0B 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1
PC3200U- 30331 Rev. 1.0 HEX 80 08 07 0D 0B 02 48 00 04 50 70 02 82 08 08 01 0E 04 1C 01 02 20 C1
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
HYS64D128320HU-5-C
HYS64D128320HU-6-C
HYS72D128320HU-5-C
Product Type
Organization
1 GByte x64
1 GByte x64
1 GByte x72
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 Description tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) PC3200U- 30331 Rev. 1.0 HEX 60 70 75 70 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 00 10 B0 7F 7F PC2700U- 25331 Rev. 1.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 01 00 10 54 7F 7F PC3200U- 30331 Rev. 1.0 HEX 60 70 75 70 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 00 10 C2 7F 7F PC2700U- 25331 Rev. 1.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 01 00 10 66 7F 7F
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HYS72D128320HU-6-C
Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
HYS64D128320HU-5-C
HYS64D128320HU-6-C
HYS72D128320HU-5-C
Product Type
Organization
1 GByte x64
1 GByte x64
1 GByte x72
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Description Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code PC3200U- 30331 Rev. 1.0 HEX 7F 7F 7F 51 00 00 xx 36 34 44 31 32 38 33 32 30 48 55 35 43 20 20 20 20 20 1x PC2700U- 25331 Rev. 1.0 HEX 7F 7F 7F 51 00 00 xx 36 34 44 31 32 38 33 32 30 48 55 36 43 20 20 20 20 20 1x PC3200U- 30331 Rev. 1.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 30 48 55 35 43 20 20 20 20 20 1x PC2700U- 25331 Rev. 1.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 30 48 55 36 43 20 20 20 20 20 1x
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HYS72D128320HU-6-C
Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
HYS64D128320HU-5-C
HYS64D128320HU-6-C
HYS72D128320HU-5-C
Product Type
Organization
1 GByte x64
1 GByte x64
1 GByte x72
1 GByte x72
2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 92 93 94 95 - 98 Description Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number PC3200U- 30331 Rev. 1.0 HEX xx xx xx xx 00 PC2700U- 25331 Rev. 1.0 HEX xx xx xx xx 00 PC3200U- 30331 Rev. 1.0 HEX xx xx xx xx 00 PC2700U- 25331 Rev. 1.0 HEX xx xx xx xx 00
99 - 127 Not used
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HYS72D128320HU-6-C
Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
5
Package Outlines
FIGURE 8
Package Outline UDIMM Raw Card C (L-DIM-184-18)
0.1 A B C
Package Outline for HYS64D32301HU-[5/6]-C
133.35 128.95
0.15 A B C 2.7 MAX.
A
1)
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Package Outline for HYS64D64300HU-[5/6]-C
FIGURE 9
Package Outline UDIMM Raw Card A (L-DIM-184-32)
0.1 A B C
133.35 128.95
0.15 A B C 2.7 MAX.
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Package Outline for HYS72D64300HU-[5/6]-C
FIGURE 10
Package Outline UDIMM Raw Card A (L-DIM-184-30)
0.1 A B C
133.35 128.95
0.15 A B C 2.7 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
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Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Package Outline for HYS[64/72]D128320HU-[5/6]-C
FIGURE 11
Package Outline UDIMM Raw Card B (L-DIM-184-31)
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Rev. 1.21, 2006-09 03292006-RA8T-MSZL
43
Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules
Table of Contents
1 1.1 1.2 2 3 3.1 3.2 3.3 4 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 18 21
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Rev. 1.21, 2006-09 03292006-RA8T-MSZL
39
Internet Data Sheet
Edition 2006-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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